This disclosure relates to systems and methods for calibrating a Data Strobe (DQS) enable/disable signal and for tracking the timing of the DQS enable/disable signal with respect to changes in voltage and temperature (VT) in order to improve the timing margin of the DQS enable/disable signal in programmable devices using Double Data Rate (DDR) memory.
DDR Synchronous Dynamic Random Access Memory (DDR SDRAM) is a type of memory that operates at twice the data transfer rate of Synchronous Dynamic RAM (SDRAM). In SDRAM, data (DQ) input/output is synchronized with the rising edges of a clock signal. In DDR SDRAM, data input/output is synchronized with both the rising and falling edges of the clock. Specifically, DDR SDRAM utilizes a DQS signal, which has the same period as the clock, to synchronize the data input/output.
DQS is a bi-directional strobe signal that functions as the operating clock for DQ during both read and write operations. DQS is a tri-state logic signal, i.e., DQS can have one of three signal values—high-impedance, logic low, or logic high. DQS is generally in a high-impedance state when it is not required. When a command is received to perform a read operation, DQS switches from the high-impedance state to a logic low signal value approximately one clock cycle prior to data output. The duration during which DQS has a logic low signal level is referred to as a preamble. A DQS enable signal may be generated such that the DQS enable signal becomes high logic in the middle of the DQS preamble period. Similarly, once the read operation is complete, after approximately half a clock cycle of the last falling edge of DQS, DQS reverts back to a high-impedance state. The duration of time after the read operation is complete and before DQS reverts back to a high-impedance state is referred to as a postamble. A DQS disable signal may be generated at some time during the postamble period to prevent DQS from being utilized when it is in the high-impedance state.
As the performance requirements of DDR SDRAM increase, e.g., as DDR SDRAM is required to support higher data rates, the timing requirements of the DQS enable/disable signal become more stringent because the DQS frequency increases and the time window during which the DQS enable/disable signal may be generated becomes smaller. In some instances, the timing margin of the DQS enable/disable signal shrinks faster than the timing margin of the read/write operations. This makes it challenging to generate the DQS enable/disable signal accurately.
DQS and DQ are generally source synchronous signals, i.e., DQS and DQ are both generated based on the same clock signal and typically have the same routing path. This implies that if there is any jitter in the clock signal then both DQS and DQ are affected equally. Therefore, the timing of DQS relative to DQ does not change significantly. In contrast, the DQS enable/disable signal is not a source synchronous signal, i.e., it is not generated based on the same clock signal as DQS and DQ. Therefore, the DQS enable/disable signal is susceptible to jitter relative to the DQS and DQ signals. The DQS enable/disable signal is also susceptible to VT variations. These aspects of the DQS enable/disable signal add to the challenge of generating it accurately.